The present invention relates to burst frame phase synchronization, which provides measures to prevent erroneous synchronization when synchronism is to be acquired for burst data.
Conventionally, the burst frame phase synchronizing circuit has been used particularly as one of the systems for protection against erroneous synchronization for burst data in an ATM burst multiplex transmission art. The erroneous synchronization protective system of this kind is used for the purpose of preventing entering of erroneous synchronization and longer pull-in time for the error of the transmission line of a transmission device.
As an example, FIG. 5 illustrates the circuitry of "a frame synchronizing circuit" disclosed in JP-A-(No. 2-10617/(1990).
Referring to FIG. 5, a received data string DATA is input to a clock signal reproducing circuit 21 and a frame synchronizing pattern comparator circuit 22, and received data RD is input to a burst error detecting circuit 23. The output of the reproduced clock signal CLOCK of the clock signal reproducing circuit 21 is connected to the frame synchronizing pattern comparator circuit 22, a frame counter 24 and a frame synchronizing window output circuit 25.
The outputs of the counter signals A0 to A7 of the frame counter 24 are connected to the frame synchronizing window output circuit 25. The output of the coincidence signal PDET of the frame synchronizing pattern comparator circuit 22 and the output of the frame synchronizing signal WINDOW of the frame synchronizing window output circuit 25 are respectively connected to the inputs of an AND gate 26.
The output of the frame synchronizing pattern detecting signal FDET of the AND gate 26 is connected to a frame synchronizing window length selecting circuit 27 and a frame synchronization protective circuit 28.
The output of the counter signal B0 of the frame counter 24 is connected to the frame synchronization protective circuit 28, and a frame synchronizing signal FSYNC is sent out from the frame counter 24.
The output of the hunting mode signal HUNT of the frame synchronization protective circuit 28 is connected to the frame synchronizing window length selecting circuit 27, and the output of a reset signal RESET is connected to the frame counter 24.
The output of the selecting signal SELECT of the frame synchronizing window selecting circuit 27 is connected to the frame synchronizing window output circuit 25.
The frame synchronizing circuit constructed in the foregoing manner stops a synchronization protecting operation (forward protecting operation) for a burst error generated during establishing of synchronization and monitors synchronization by widening a synchronization monitoring window when the burst error is finished. In this way, shifting or erroneous synchronization is prevented and thereby a correct synchronizing phase can be quickly recovered.
In the conventional example, however, synchronization must be re-established for a burst signal each time input burst occurs and it is meaningless to hold synchronization for an error. Accordingly, when an input signal is given in a burst condition, this system cannot process this signal.
Furthermore, in the case of burst multiplexed data, a limit is placed on the fluctuation range of a signal in order to reduce overheads for data by a synchronizing signal. In this condition, widening of the synchronization monitoring window is not effective. Accordingly, it is obvious that a problem is inherent in this conventional system. Specifically, a synchronism acquiring characteristic cannot be improved even by widening the range of synchronization monitoring.